1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to semiconductor chip capacitors and methods of making the same.
2. Description of the Related Art
Conventional integrated circuits use capacitors for a variety of purposes, such as data storage, low pass, high pass and band pass signal filtering, and power rail decoupling. Some types of capacitors are manufactured as discrete components that are designed to be connected externally to a semiconductor chip. Typical semiconductor chip package substrate capacitors are an example of the discrete variety. Other types of semiconductor chip capacitors are built directly into the semiconductor chip. These on-die capacitors tend to be smaller than, and thus more constrained by the pressures of device scaling, than their off-chip counterparts.
One type of conventional capacitor design consists of a stack that has several levels of conductor plates. Two plates in a given level include interwoven conductive strips that form a structure that resembles a pair of hair combs meshed together teeth-to-teeth. The interwoven strips are straight rectangular structures.
The capacitance of almost all types of capacitors is a function of the dielectric constant of the medium separating the capacitor plates, the area of overlap of the capacitor plates, and the spacing between the capacitor plates. For the comb-style capacitor described above, the total capacitance is a sum of inter plate capacitance and another form of capacitance known as fringe capacitance. Both the inter plate capacitance and the fringe capacitance are proportional to plate overlap area. However, the overlap areas for the two types of capacitance are usually in two different but orthogonal planes.
Device scaling in semiconductor chip manufacturing is an almost ever present goal of integrated circuit designers. As the critical dimensions of lithographic fabrication processes continue to fall, devices other than transistors, resistors and conductor lines must also scale downward. For on-chip capacitors, device scaling represents a challenge. The goal is to at least maintain acceptable levels of total available on-chip capacitance while simultaneously shrinking the size of individual capacitors. Better dielectrics may be used, but not without material and manufacturing costs. Plate spacings could be lowered, but at greater risks of dielectric breakdown.
One conventional technique for improving decoupling involves providing more raw capacitance on the die. However, this technique may be severely constrained by the requirements of packing density or will lead to die size growth.
The present invention is directed to overcoming some of the aforementioned challenges.